The CDCV857ADGGR is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs. When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857ADGGR is also able to track spread spectrum clocking for reduced EMI. Since the CDCV857ADGGR is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857ADGGR is characterized for operation from 0?C to 85?C.Features:Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 60 to 180 MHzLow Jitter (cyc?cyc): ?50 psDistributes One Differential Clock Input to Ten Differential Outputs3-State Outputs When the Input Differential Clocks Are
