These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. They have an asynchronous clear input, and feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Features:Advanced oxide-isolated ion-implanted Schottky TTL processPin and functional compatible with LS family counterpartTypical clock frequency maximum is 80 MHzSwitching performance guaranteed over full temperature and VCC supply range16 pin DIP. Actual brand may vary from picture.G4692A
