カテゴリ: 論文誌(論文単位)グループ名: 【C】電子・情報・システム部門発行日: 2017/02/01タイトル(英語): Stochastic TDC Architecture with Self-Calibration and its RTL Verification著者名: Congbing Li (Division of Electronics and Informatics, Gunma University), Junshan Wang (Division of Electronics and Informatics, Gunma University), Haruo Kobayashi (Division of Electronics and Informatics, Gunma University), Ryoji Shiota (Socionext Inc.)著者名(英語): Congbing Li (Division of Electronics and Informatics, Gunma University), Junshan Wang (Division of Electronics and Informatics, Gunma University), Haruo Kobayashi (Division of Electronics and Informatics, Gunma University), Ryoji Shiota (Socionext Inc.)キーワード: Timing Measurement，Stochastic，Time to Digital Converter，Self-calibration，FPGA要約(英語): A time-to-digital converter (TDC) based on stochastic process and statistics theory is presented. This architecture utilizes the stochastic variation in CMOS process positively for fine time resolution. It needs a large number of flip-flops for statistics but advanced fine CMOS technology can realize it. The self-calibration technique using the histogram method is applied to compensate the nonlinearity due to the circuit characteristics variation as well as timing skew by layout and routing. The proposed TDC can be implemented with full digital circuit, which is suitable as nano-CMOS mixed-signal circuit. Register-Transfer-Level (RTL) simulation is conducted to validate the operation principle. RTL verification results indicate that the proposed stochastic architecture with self-calibration feature can realize a linear TDC with sub-picosecond time resolution.本誌: 電気学会論文誌C（電子・情報・システム部門誌） Vol.137 No.2 （2017） 大特集：電子・情報・システム部門誌 30周年記念「電子・情報・システム技術によるイノベーション」本誌掲載ページ: 335-341 p原稿種別: 論文／英語電子版へのリンク: https://www.jstage.jst.go.jp/article/ieejeiss/137/2/137_335/_article/-char/ja/
