Jean-Loup BaerCambridge University Press, 12/7/2009EAN 9780521769921, ISBN10: 0521769922Hardcover, 382 pages, 25.3 x 21.5 x 2.5 cmLanguage: EnglishThis book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.1. Introduction2. The basics3. Superscalar processors4. Front-endbranch prediction, instruction fetching, and register renaming5. Back-endinstruction scheduling, memory access instructions, and clusters6. The cache hierarchy7. Multiprocessors8. Multithreading and (chip) multiprocessors9. Current limitations and future challenges.
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