The board has been designed to support a range of developments from simple logic and embedded system development, to more complex solutions such as image processing. FEATURES AMD Spartan 7 XC7S50 with 52160 logic cells, 75 BRAM, 5 CMT, 120 DSP48 REFERENCES Reference Designs, XDC, Schematics, Vivado board definition can be found here APPLICATION EXAMPLES INCLUDE RPI_FPGA_UART_AXI Vivado 2023.2 Configures a UART in the RP2040 to communicate with the FPGA, sending a protocol over the UART and IP in the FPGA AXI peripherals can be accessed and controlled. In this version three AXI GPIO are connected to three LEDS, the final LED is connected to a AXI timer to demonstrate PWM on the LED. The 4 slide switches are also connected to the AXI GPIO to enable their status to be read over the AXI GPIO. Refer to project here for detials on protocol SDRAM Vivado 2023.2 - SDRAM example for the SDRAM on the board. MBV_MCS Vivado & Vitis 2024.1 MicroBlaze V (RISC-V) MicroController System implemented on the Spartan 7 see blog S7_LEO Vivado 2023.2 IO check of all FPGA PMOD IO and 4 LED, walks a LED around all 28 LEDS (4 on board, 24 on Pmod LED - not included) - also connects through the user flash to the RPI for testing DELTA_SIGMA Vivado 2024.1 Delta Sigma output at 1KHz on PMod 1 pin 1, PWM Sine output at 1 KHz on Pmod 1 pin 2, - external RC needed for recovery LEARN MORE ABOUT THE BOARD IN THESE BLOGS https://www.adiuvoengineering.com/post/microzed-chronicles-leonidas-board https://www.adiuvoengineering.com/post/microzed-chronicles-spartan-7-and-axi-over-uart https://www.adiuvoengineering.com/post/microzed-chronicles-microblaze-v-mcs https://www.adiuvoengineering.com/post/microzed-chronicles-vivado-board-definitions
